View ICS87322BI_283547.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
FEATURES
* 15 differential LVPECL outputs * Selectable LVPECL differential clock inputs * CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Output frequency: 750MHz (maximum) * Output skew: 180ps (maximum) * Bank skew: 65ps (maximum) * Part-to-part skew: 500ps (maximum) * LVPECL mode operating voltage supply range: VCC = 3V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -3V * -40C to 85C ambient operating temperature * Lead-Free package fully RoHS compliant
ICS87322BI
GENERAL DESCRIPTION
The ICS87322BI is a low skew, /1//2 3.3V LVPECL/ECL Clock Generator and a member of HiPerClockSTM the HiPerClockSTM family of High Performance Clock Solutions from ICS. Using multiplexed/ redundant clock inputs the ICS87322BI is designed to translate most differential signal levels to LVPECL/ ECL levels.
ICS
The CLK_SEL input selects between CLK0, nCLK0 and CLK1, nCLK1 as the active input. The divide select inputs, DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset input can be used to reset the internal dividers and disable the clock outputs. Disabled outputs QAx, QBx, QCx and QDx will be forced low. Disabled outputs nQAx, nQBx, nQCx and nQDx will be forced high. The ICS87322BI is characterized across the industrial temperature range and over the supply voltage range of 3V to 3.8V for LVPECL and -3.8V to -3V for LVECL/ECL. Guaranteed output and part to part skew characteristics make the ICS87322BI an excellent choice for clock generator and clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
MR CLK0 nCLK0 CLK1 nCLK1 CLK_SEL DIV_SELA 0 1 DIV_SELB 0 1 DIV_SELC 0 1 DIV_SELD
6 4 3
PIN ASSIGNMENT
nQC0 nQC1 nQC2 nQC3 VCCO VCCO
VCCO 0 1
2
39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 41 42 43 44 45 46 47 48 49 50 51 52 1
VCC
VCCO
QC0
QC1
QC2
QC3
nc
nc
QD0 nQD0 QD1 nQD1 QD2 nQD2 QD3 nQD3 QD4 nQD4 QD5 nQD5 VCCO
QA0:1 nQA0:1
nQB2 QB2 nQB1 QB1 nQB0 QB0
25 24 23 22 21
QB0:2 nQB0:2
ICS87322BI
20 19 18 17 16 15
VCCO nQA1 QA1 nQA0 QA0 VCCO
QC0:3 nQC0:3
23
DIV_SELA MR
4
DIV_SELB
5
CLK0
6
nCLK0
14 7 8 9 10 11 12 13
CLK1 DIV_SELC DIV_SELD CLK_SEL nCLK1 VEE nc
QD0:5 nQD0:5
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View
87322BYI
www.icst.com/products/hiperclocks.html
1
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
Type Power Input Pulldown Description Core supply pin. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inver ted outputs (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Selects divide value for Bank A output as described in Table 3C. LVCMOS / LVTTL interface levels. Selects divide value for Bank B output as described in Table 3C. LVCMOS / LVTTL interface levels. Non-inver ting differential LVPECL clock input. LVPECL interface levels.
ICS87322BI
TABLE 1. PIN DESCRIPTIONS
Number 1 2 Name VCC MR
3 4 5 6 7 8 9 10, 28, 29 11 12 13 14, 27, 30, 39, 40, 47, 52 15,16 17, 18 19, 20 2 1, 22 23, 24 25, 26 31, 32 33, 34 3 5, 36 37, 38 41, 42 43, 44 45, 46 48, 49 50, 51
DIV_SELA DIV_SELB CLK0 nCLK0 CLK_SEL CLK1 nCLK1 nc DIV_SELC DIV_SELD VEE VCCO nQD5, QD5 nQD4, QD4 nQD3, QD3 nQD2, QD2 nQD1, QD1 nQD0, QD0 nQC3, QC3 nQC2, QC2 nQC1, QC1 nQC0, QC0 nQB2, QB2 nQB1, QB1 nQB0, QB0 nQA1, QA1 nQA0, QA0
Input Input Input Input Input Input Input Unused Input Input Power Power Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
Pulldown Pulldown Pulldown Pullup
Inver ting differential LVPECL clock input. LVPECL interface levels. Clock select. When HIGH, selects CLK1, nCLK1 inputs. When LOW, Pulldown selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input. LVPECL interface levels. Pullup Inver ting differential LVPECL clock input. LVPECL interface levels. No connect. Selects divide value for Bank C output as described in Table 3C. Pulldown LVCMOS / LVTTL interface levels. Selects divide value for Bank D output as described in Table 3C. Pulldown LVCMOS / LVTTL interface levels. Negative supply pin. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87322BYI
www.icst.com/products/hiperclocks.html
2
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
Test Conditions CLKx, nCLKx CLK_SEL, DIV_SELx, MR Minimum Typical 2 4 51 51 Maximum Units pF pF k k
ICS87322BI
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs MR CLK_SEL 1 0 0 X 0 1 QA0:QA1 LOW Active Active nQA0:nQA1 QB0:QB2 HIGH Active Active LOW Active Active HIGH Active Active Outputs nQB0:nQB2 QC0:QC3 LOW Active Active nQC0:nQC3 HIGH Active Active QD0:QD5 LOW Active Active nQD0:nQD5 HIGH Active Active
TABLE 3B. INPUT CONTROL FUNCTION TABLE
Inputs CLK_SEL 0 1 Clock Input CLK0, nCLK0 CLK1, nCLK1
TABLE 3C. SELECT PIN FUNCTION TABLE
Inputs SEL_A SEL_B 0 1 0 1 SEL_C 0 1 SEL_D 0 1 QAx /1 /2 Outputs QBx /1 /2 QCx /1 /2 QDx /1 /2
CLK
MR
Q /1 nQ /1
Q /2 nQ /2
FIGURE 1. TIMING DIAGRAM
www.icst.com/products/hiperclocks.html
3
87322BYI
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 42.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ICS87322BI
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3V TO 3.8V, TA = -40C TO 85C
Symbol VCC VCCO IEE ICCO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.0 3.0 Typical 3.3 3.3 Maximum 3.8 3.8 160 98 Units V V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO = 3V TO 3.8V, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current MR, CLK_SEL, F_SELA:F_SELD MR, CLK_SEL, F_SELA:F_SELD MR, CLK_SEL, F_SELA:F_SELD MR, CLK_SEL, F_SELA:F_SELD Test Conditions Minimum 2 Typical Maximum VCC + 0.3 0.8 VCC = VIN = 3.8V VIN = 0V, VCC = 3.8V -5 150 Units V V A A
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3V TO 3.8V, TA = -40C TO 85C
Symbol IIH IIL VPP VCMR VOH VOL Parameter Input High Current Input Low Current CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 Test Conditions VCC = VIN =3.8V VCC = VIN =3.8V VIN = 0V, VCC = 3.8V VIN = 0V, VCC = 3.8V -5 -150 0.15 VEE + 1.5 VCC - 1.4 VCC - 2.0 1.0 VCC VCC - 1.0 VCC - 1.7 Minimum Typical Maximum 15 0 5 Units A A A A V V V V V
Peak-to-Peak Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage, NOTE 3 Output Low Voltage, NOTE 3
Peak-to-Peak Output Voltage Swing 0.6 1. 0 VSWING NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, CLK1 is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCCO - 2V.
87322BYI
www.icst.com/products/hiperclocks.html
4
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
Test Conditions Minimum 1.5 = 212MHz Typical Maximum 750 2.7 180 150 65 500 Units MHz ns ps ps ps ps ps
ICS87322BI
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3V TO 3.8V, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 5 Bank Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 4, 5
tsk(o) tsk(b) tsk(pp)
tR / tF Output Rise/Fall Time 20% to 80% 150 600 All parameters measured at 750MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2:Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO/2. NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VCCO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
87322BYI
www.icst.com/products/hiperclocks.html
5
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
ICS87322BI
PARAMETER MEASUREMENT INFORMATION
2V V CC VCC , VCCO
Qx
SCOPE
nCLK0, nCLK1 V
PP
LVPECL
VEE
nQx
Cross Points
V
CMR
CLK0, CLK1 VEE
-1.8V to -1.0V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx Qx nQy Qy
tsk(o)
nQx Qx
PART 2
nQy Qy
tsk(pp)
OUTPUT SKEW
nQXx
PART-TO-PART SKEW
80% QXx nQXy QXy
tsk(b)
80% VSW I N G
Clock Outputs
20% tR tF
20%
Where X = A, B, C or D
BANK SKEW
nCLK0, nCLK1 CLK0, CLK1 nQx Qx
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
87322BYI
www.icst.com/products/hiperclocks.html
6
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR APPLICATION INFORMATION
ICS87322BI
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
Zo = 50
3.3V 125 125
FOUT
FIN
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
87322BYI
FIGURE 3B. LVPECL OUTPUT TERMINATION
REV. B JUNE 20, 2005
www.icst.com/products/hiperclocks.html
7
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
ICS87322BI
LVPECL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm 2.5V
2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120
R2 50
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
R1 120 R2 120
nPCLK
HiPerClockS PCLK/nPCLK
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
Zo = 50 Ohm R5 100 C2 3.3V Zo = 50 Ohm LVDS C1
3.3V 3.3V R3 1K R4 1K PCLK
R4 125
nPCLK
HiPerClockS PC L K/n PCL K
R1 1K
R2 1K
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 4E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
87322BYI
www.icst.com/products/hiperclocks.html
8
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
capacitors should be physically located near the power pin. For ICS87322BI, the unused outputs can be left floating.
ICS87322BI
SCHEMATIC EXAMPLE
Figure 5 shows a schematic example of the ICS87322BI. In this example, the CLK0/nCLK0 input is selected. The input is driven by an LVPECL driver. All banks are set at /2. The decoupling
VCC RU3 SP RU4 1K RU5 1K RU6 1K RU7 1K CLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD RD3 1K 3.3V Zo = 50 DIV_SELA DIV_SELB CLK_SEL Zo = 50 LVPECL R1 50 R2 50 R3 50 DIV_SELC DIV_SELD RD4 SP RD5 SP RD6 SP RD7 SP 1 2 3 4 5 6 7 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 42 41 40 Zo = 50 VCC U1 ICS87322I R4 50 R5 50
SP = Spare (i.e. not intstalled)
Zo = 50 +
-
VCCO QA0 nQA0 QA1 nQA1 VCCO QB0 nQB0 QB1 nQB1 QB2 nQB2 VCCO
VCC MR DIV_SELA DIV_SELB CLK0 nCLK0 CLK_SEL CLK1 nCLK1 nc DIV_SELC DIV_SELD VEE VCCO nQD5 QD5 nQD4 QD4 nQD3 QD3 nQD2 QD2 nQD1 QD1 nQD0 QD0
VCCO QC0 nQC0 QC1 nQC1 QC2 nQC2 QC3 nQC3 VCCO nc nc VCCO
39 38 37 36 35 34 33 32 31 30 29 28 27
R6 50
14 15 16 17 18 19 20 21 22 23 24 25 26
Zo = 50 +
Zo = 50 R8 50 R7 50
-
(U1-1)
VCC
(U1-14)
(U1-27)
(U1-30)
(U1-39)
(U1-40)
(U1-47)
(U1-52)
C1 0.1uF
C2 0.1uF
C3 0.1uF
C4 0.1uF
C5 0.1uF
C6 0.1uF
C7 0.1uF
C8 0.1uF
R9 50
Bypass capacitors located near the power pins
FIGURE 5. ICS87322BI SCHEMATIC EXAMPLE
87322BYI
www.icst.com/products/hiperclocks.html
9
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR POWER CONSIDERATIONS
ICS87322BI
This section provides information on power dissipation and junction temperature for the ICS87322BI. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS87322BI is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 160mA = 608mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 15 * 30.2mW = 453mW
Total Power_MAX (3.8V, with all outputs switching) = 608mW + 453mW = 1061mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36.4C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 1.061W * 36.4C/W = 123.6C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
52-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0C/W 42.3C/W
200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
87322BYI
www.icst.com/products/hiperclocks.html
10
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
ICS87322BI
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
87322BYI
www.icst.com/products/hiperclocks.html
11
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR RELIABILITY INFORMATION
ICS87322BI
TABLE 7.
JAVS. AIR FLOW TABLE FOR 52 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0 200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
58.0C/W 42.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87322BI is: 1331 Pin compatible with the MC100LVE222
87322BYI
www.icst.com/products/hiperclocks.html
12
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
52 LEAD LQFP
ICS87322BI
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 E E1 e L ccc 0.45 0 --0.05 1.35 0.22 0.09 BCC MINIMUM NOMINAL 52 --1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC ---0.75 7 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026 www.icst.com/products/hiperclocks.html
13
87322BYI
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
ICS87322BI
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS87322BYI ICS87322BYIT ICS87322BYILF ICS87322BYILFT Marking ICS87322BYI ICS87322BYI ICS87322BYILF ICS87322BYILF Package 52 Lead LQFP 52 Lead LQFP 52 Lead "Lead-Free" LQFP 52 Lead "Lead-Free" LQFP Shipping Packaging tray 500 tape & reel tray 500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87322BYI
www.icst.com/products/hiperclocks.html
14
REV. B JUNE 20, 2005
Integrated Circuit Systems, Inc.
LOW SKEW, /1//2, 3.3V LVPECL/ECL CLOCK GENERATOR
REVISION HISTORY SHEET
ICS87322BI
Rev
Table
Page
T4A T4B T4C B T5B
4 4 4
5 6 8 9 1 2 14 14 6
B B B
T2 T9 T9
Description of Change Changed input levels to LVPECL throughout data sheet. Changed operating supply range from 2.375V to 3V throughout data sheet. Power Supply table - changed VCC & VCCO from 2.375V min. to 3V min. LVCMOS table - deleted 2.625V test conditions. Changed Differential table to a LVPECL table. Deleted 2.625V test conditions. Revised VCMR min. from VEE + 0.5V to VEE + 1.5V and max. from VCC - 0.85V to VCC. Deleted Table 5B, 2.5V AC Characteristics table. Revised Output Load AC Test Circuit Diagram, VEE. Deleted Termination for 2.5V LVPECL Output. Changed Differential Clock Input Interface to LVPECL Clock Input Interface. (Now page 8.) Features section - added Lead-Free bullet. Pin Description Table - added pin 30 (VCCO). Ordering Information Table - added Lead-Free par t number. Ordering Information Table - added Lead-Free marking. Corrected Output Load AC Test Circuit Diagram - VEE = -1.8V to 1.0V from ...to -0.375V.
Date
4/6/04
5/11/05 6/9/05 6/20/05
87322BYI
www.icst.com/products/hiperclocks.html
15
REV. B JUNE 20, 2005

▲Up To Search▲

Price & Availability of ICS87322BI

	To Download ICS87322BI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .